外设中断ID： /******Cortex-M3 Processor Exceptions Numbers ***************************************************/CMSIS中的中断定义
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt 非屏蔽中断 */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management InterruptCortex-M3内存管理中断 */
BusFault_IRQn= -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn= -10, /*!< 6 Cortex-M3 Usage Fault Interrupt*/
SVCall_IRQn= -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt*/
PendSV_IRQn= -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn= -1, /*!< 15 Cortex-M3 System Tick Interrupt */
/******STM32 specific Interrupt Numbers *********************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt*/
PVD_IRQn= 1, /*!< PVD through EXTI Line detection Interrupt */
TAMPER_IRQn= 2, /*!< Tamper Interrupt */
RTC_IRQn= 3, /*!< RTC global Interrupt */
FLASH_IRQn= 4, /*!< FLASH global Interrupt */
RCC_IRQn= 5, /*!< RCC global Interrupt */
EXTI0_IRQn= 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn= 7, /*!< EXTI Line1 Interrupt */
EXTI2_IRQn= 8, /*!< EXTI Line2 Interrupt */
EXTI3_IRQn= 9, /*!< EXTI Line3 Interrupt */
EXTI4_IRQn= 10, /*!< EXTI Line4 Interrupt */
DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
#ifdef STM32F10X_LD
ADC1_2_IRQn= 18, /*!< ADC1 and ADC2 global Interrupt */
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
CAN1_RX1_IRQn= 21, /*!< CAN1 RX1 Interrupt */
CAN1_SCE_IRQn= 22, /*!< CAN1 SCE Interrupt */
EXTI9_5_IRQn= 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_IRQn= 24, /*!< TIM1 Break Interrupt */
TIM1_UP_IRQn= 25, /*!< TIM1 Update Interrupt*/
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt*/
TIM1_CC_IRQn= 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt*/
TIM3_IRQn = 29, /*!< TIM3 global Interrupt*/
I2C1_EV_IRQn= 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn= 32, /*!< I2C1 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt*/
USART1_IRQn= 37, /*!< USART1 global Interrupt*/
USART2_IRQn= 38, /*!< USART2 global Interrupt*/
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn= 41, /*!< RTC Alarm through EXTI Line Interrupt*/
USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
#endif /* STM32F10X_LD */
#ifdef STM32F10X_LD_VL
ADC1_IRQn = 18, /*!< ADC1 global Interrupt*/
EXTI9_5_IRQn= 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
TIM1_CC_IRQn= 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt*/
TIM3_IRQn = 29, /*!< TIM3 global Interrupt*/
I2C1_EV_IRQn= 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn= 32, /*!< I2C1 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt*/
USART1_IRQn= 37, /*!< USART1 global Interrupt*/
USART2_IRQn= 38, /*!< USART2 global Interrupt*/
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn= 41, /*!< RTC Alarm through EXTI Line Interrupt*/
CEC_IRQn= 42, /*!< HDMI-CEC Interrupt */
TIM6_DAC_IRQn= 54, /*!< TIM6 and DAC underrun Interrupt */
TIM7_IRQn = 55 /*!< TIM7 Interrupt */
#endif /* STM32F10X_LD_VL */
这里是STM32比较重要的头文件
系统异常ID：
外设中断ID： #ifdef STM32F10X_MD這是我們前面講過的不同的芯片型號，對應 著不同的中斷級別。請大家自行研究！
ADC1_2_IRQn= 18, /*!< ADC1 and ADC2 global Interrupt */
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
CAN1_RX1_IRQn= 21, /*!< CAN1 RX1 Interrupt */
CAN1_SCE_IRQn= 22, /*!< CAN1 SCE Interrupt */
EXTI9_5_IRQn= 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_IRQn= 24, /*!< TIM1 Break Interrupt */
TIM1_UP_IRQn= 25, /*!< TIM1 Update Interrupt*/
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt*/
TIM1_CC_IRQn= 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt*/
TIM3_IRQn = 29, /*!< TIM3 global Interrupt*/
TIM4_IRQn = 30, /*!< TIM4 global Interrupt*/
I2C1_EV_IRQn= 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn= 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn= 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn= 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt*/
SPI2_IRQn = 36, /*!< SPI2 global Interrupt*/
USART1_IRQn= 37, /*!< USART1 global Interrupt*/
USART2_IRQn= 38, /*!< USART2 global Interrupt*/
USART3_IRQn= 39, /*!< USART3 global Interrupt*/
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn= 41, /*!< RTC Alarm through EXTI Line Interrupt*/
USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
#endif /* STM32F10X_MD */
#ifdef STM32F10X_MD_VL這是我們前面講過的不同的芯片型號，對應 著不同的中斷級別。請大家自行研究！
ADC1_IRQn = 18, /*!< ADC1 global Interrupt*/
EXTI9_5_IRQn= 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
TIM1_CC_IRQn= 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt*/
TIM3_IRQn = 29, /*!< TIM3 global Interrupt*/
TIM4_IRQn = 30, /*!< TIM4 global Interrupt*/
I2C1_EV_IRQn= 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn= 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn= 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn= 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt*/
SPI2_IRQn = 36, /*!< SPI2 global Interrupt*/
USART1_IRQn= 37, /*!< USART1 global Interrupt*/
USART2_IRQn= 38, /*!< USART2 global Interrupt*/
USART3_IRQn= 39, /*!< USART3 global Interrupt*/
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn= 41, /*!< RTC Alarm through EXTI Line Interrupt*/
CEC_IRQn= 42, /*!< HDMI-CEC Interrupt */
TIM6_DAC_IRQn= 54, /*!< TIM6 and DAC underrun Interrupt */
TIM7_IRQn = 55 /*!< TIM7 Interrupt */
#endif /* STM32F10X_MD_VL */ 外设中断ID： #ifdef STM32F10X_HD 這是我們前面講過的不同的芯片型號，對應 著不同的中斷級別。請大家自行研究！
ADC1_2_IRQn= 18, /*!< ADC1 and ADC2 global Interrupt */
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
CAN1_RX1_IRQn= 21, /*!< CAN1 RX1 Interrupt */
CAN1_SCE_IRQn= 22, /*!< CAN1 SCE Interrupt */
EXTI9_5_IRQn= 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_IRQn= 24, /*!< TIM1 Break Interrupt */
TIM1_UP_IRQn= 25, /*!< TIM1 Update Interrupt*/
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt*/
TIM1_CC_IRQn= 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt*/
TIM3_IRQn = 29, /*!< TIM3 global Interrupt*/
TIM4_IRQn = 30, /*!< TIM4 global Interrupt*/
I2C1_EV_IRQn= 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn= 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn= 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn= 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt*/
SPI2_IRQn = 36, /*!< SPI2 global Interrupt*/
USART1_IRQn= 37, /*!< USART1 global Interrupt*/
USART2_IRQn= 38, /*!< USART2 global Interrupt*/
USART3_IRQn= 39, /*!< USART3 global Interrupt*/
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTCAlarm_IRQn= 41, /*!< RTC Alarm through EXTI Line Interrupt*/
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
TIM8_BRK_IRQn= 43, /*!< TIM8 Break Interrupt */
TIM8_UP_IRQn= 44, /*!< TIM8 Update Interrupt*/
TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt*/
TIM8_CC_IRQn= 46, /*!< TIM8 Capture Compare Interrupt */
ADC3_IRQn = 47, /*!< ADC3 global Interrupt*/
FSMC_IRQn = 48, /*!< FSMC global Interrupt*/
SDIO_IRQn = 49, /*!< SDIO global Interrupt*/
TIM5_IRQn = 50, /*!< TIM5 global Interrupt*/
SPI3_IRQn = 51, /*!< SPI3 global Interrupt*/
UART4_IRQn= 52, /*!< UART4 global Interrupt */
UART5_IRQn= 53, /*!< UART5 global Interrupt */
TIM6_IRQn = 54, /*!< TIM6 global Interrupt*/
TIM7_IRQn = 55, /*!< TIM7 global Interrupt*/
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
#endif /* STM32F10X_HD */
#include "core_cm3.h"STM32的内核是ARM CORTEX-M3，这个core_cm3.h包含的是一些内核相关的函数和宏定义，例如核内寄存器定义、部分核内外设的地址等等，其对应的是core_cm3.c文件。初学可以不管他，只要把它包含进工程里就行了，这里都是非常底层的函数，上层的一些函数直接调用它们了。如果对CORTEX-M3内核有兴趣或者基础较高，想深入了解这些函数，可以仔细研读一下,我们在后续的开讲中会仔细讲解这一个文件的内容。
#include "system_stm32f10x.h"这个文件就是我们现在所讲的文件了。
#include <stdint.h><stdint.h> 定义了 int16_t 、 uint32_t 、 int64_t 等整型，在需要确定大小的整型时可以使用它们代替 short 、 unsigned long long 等，在 C 整型中，只使用 int 。
/** @addtogroup Exported_types
* @{
*/
/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */由于新的文件与老的文件会有不兼容问题，所以要转换变量类型。
typedef int32_ts32;typedef在计算机编程语言中用来为复杂的声明定义简单的别名，与宏定义有些差异。它本身是一种存储类的关键字，与auto、extern、mutable、static、register等关键字不能出现在同一个表达式中。
《变量类型》，3.0以后的版本中使用了CMSIS数据类型，变量的定义有所不同，但是出于兼容旧版本的目的，以上的数据类型仍然兼容。
CMSIS IO类型限定词件库与CMSIS数据类型对比
stm32f10x.h文件中还包含了常用的布尔形变量定义，如：
1 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
2
3 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
4
5 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
6
7 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
不同版本的标准外设库的变量定义略有不同，如3.4版本中就没有之前版本的TRUE和FALSE的定义，用户也可以根据自己的需求按照上面的格式定义自己的布尔形变量。在使用标准外设库进行开发遇到相关的定义问题时应首先找到对应的头文件定义。
typedef int16_t s16;
typedef int8_ts8;
typedef const int32_t sc32;/*!< Read Only */
const是一个C语言的关键字，它限定一个变量不允许被改变。使用const在一定程度上可以提高程序的安全性和可靠性。另外，在观看别人代码的时候，清晰理解const所起的作用，对理解对方的程序也有一些帮助。另外CONST在其他编程语言中也有出现，如C++、PHP5、C#.net、HC08 C。
typedef const int16_t sc16;/*!< Read Only */
typedef const int8_t sc8; /*!< Read Only */
typedef __IO int32_tvs32;
typedef __IO int16_tvs16;
typedef __IO int8_t vs8;
typedef __I int32_t vsc32;/*!< Read Only */
typedef __I int16_t vsc16;/*!< Read Only */
typedef __I int8_t vsc8; /*!< Read Only */
typedef uint32_tu32;
typedef uint16_t u16;
typedef uint8_tu8;
typedef const uint32_t uc32;/*!< Read Only */
typedef const uint16_t uc16;/*!< Read Only */
typedef const uint8_t uc8; /*!< Read Only */
typedef __IO uint32_tvu32;
typedef __IO uint16_t vu16;
typedef __IO uint8_tvu8;
typedef __I uint32_t vuc32;/*!< Read Only */
typedef __I uint16_t vuc16;/*!< Read Only */
typedef __I uint8_t vuc8; /*!< Read Only */
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */
由于新的文件与老的文件会有不兼容问题，所以要转换变量类型。
#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT请大家注意这里的定义，高速外设时钟的启动时间。
#define HSE_Value HSE_VALUE
#define HSI_Value HSI_VALUE
/**
* @}
*/
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
*@briefAnalog to Digital Converter
*/
typedef structADC_TypeDef结构体的声名，看看它内部都有哪些内容。请读者注意。
ADC_TypeDef，看起来是一个结构类型，是对ADC寄存器各地址的一个定义。
{__IO就是volatileuint32_t就是32位无符号整形数。
这都是ARM公司无聊滴在CMSIS库里面定义的。STM32库1.x 2.x都没有这玩意，到了3.0以后引入了CMSIS就有了。__IO uint32_t SR;
__IO uint32_t CR1;
__IO uint32_t CR2;
__IO uint32_t SMPR1;
__IO uint32_t SMPR2;
__IO uint32_t JOFR1;
__IO uint32_t JOFR2;
__IO uint32_t JOFR3;
__IO uint32_t JOFR4;
__IO uint32_t HTR;
__IO uint32_t LTR;
__IO uint32_t SQR1;
__IO uint32_t SQR2;
__IO uint32_t SQR3;
__IO uint32_t JSQR;
__IO uint32_t JDR1;
__IO uint32_t JDR2;
__IO uint32_t JDR3;
__IO uint32_t JDR4;
__IO uint32_t DR;
} ADC_TypeDef;
/**
*@briefBackup Registers
*/
typedef struct这个结构体声明的是数据备份寄存器，它们是16位的。它可以管理防范入侵，可以存储RTC检验值，可以做数据备份。
{
uint32_tRESERVED0;
__IO uint16_t DR1; DR代表数据备份1---45
uint16_tRESERVED1;
__IO uint16_t DR2;
uint16_tRESERVED2;
__IO uint16_t DR3;
uint16_tRESERVED3;
__IO uint16_t DR4;
uint16_tRESERVED4;
__IO uint16_t DR5;
uint16_tRESERVED5;
__IO uint16_t DR6;
uint16_tRESERVED6;
__IO uint16_t DR7;
uint16_tRESERVED7;
__IO uint16_t DR8;
uint16_tRESERVED8;
__IO uint16_t DR9;
uint16_tRESERVED9;
__IO uint16_t DR10;
uint16_tRESERVED10;
__IO uint16_t RTCCR; RTC时钟校准寄存器
uint16_tRESERVED11;
__IO uint16_t CR;CR备份控制寄存器
uint16_tRESERVED12;
__IO uint16_t CSR;CSR 备份控制状态寄存器
uint16_tRESERVED13[5];
__IO uint16_t DR11;
uint16_tRESERVED14;
__IO uint16_t DR12;
uint16_tRESERVED15;
__IO uint16_t DR13;
uint16_tRESERVED16;
__IO uint16_t DR14;
uint16_tRESERVED17;
__IO uint16_t DR15;
uint16_tRESERVED18;
__IO uint16_t DR16;
uint16_tRESERVED19;
__IO uint16_t DR17;
uint16_tRESERVED20;
__IO uint16_t DR18;
uint16_tRESERVED21;
__IO uint16_t DR19;
uint16_tRESERVED22;
__IO uint16_t DR20;
uint16_tRESERVED23;
__IO uint16_t DR21;
uint16_tRESERVED24;
__IO uint16_t DR22;
uint16_tRESERVED25;
__IO uint16_t DR23;
uint16_tRESERVED26;
__IO uint16_t DR24;
uint16_tRESERVED27;
__IO uint16_t DR25;
uint16_tRESERVED28;
__IO uint16_t DR26;
uint16_tRESERVED29;
__IO uint16_t DR27;
uint16_tRESERVED30;
__IO uint16_t DR28;
uint16_tRESERVED31;
__IO uint16_t DR29;
uint16_tRESERVED32;
__IO uint16_t DR30;
uint16_tRESERVED33;
__IO uint16_t DR31;
uint16_tRESERVED34;
__IO uint16_t DR32;
uint16_tRESERVED35;
__IO uint16_t DR33;
uint16_tRESERVED36;
__IO uint16_t DR34;
uint16_tRESERVED37;
__IO uint16_t DR35;
uint16_tRESERVED38;
__IO uint16_t DR36;
uint16_tRESERVED39;
__IO uint16_t DR37;
uint16_tRESERVED40;
__IO uint16_t DR38;
uint16_tRESERVED41;
__IO uint16_t DR39;
uint16_tRESERVED42;
__IO uint16_t DR40;
uint16_tRESERVED43;
__IO uint16_t DR41;
uint16_tRESERVED44;
__IO uint16_t DR42;
uint16_tRESERVED45;
} BKP_TypeDef;
/**
* @brief Controller Area Network TxMailBox
*/
typedef struct
{
__IO uint32_t TIR;
__IO uint32_t TDTR;
__IO uint32_t TDLR;
__IO uint32_t TDHR;
} CAN_TxMailBox_TypeDef; CAN的发送邮箱寄存器的结构体定义。
/**
* @brief Controller Area Network FIFOMailBox
*/
typedef struct
{
__IO uint32_t RIR;
__IO uint32_t RDTR;
__IO uint32_t RDLR;
__IO uint32_t RDHR;
} CAN_FIFOMailBox_TypeDef;先进先出(FIFO)缓冲器，是一种寄存器。在这个头文件里定义了它的结构体类型。
/**
* @brief Controller Area Network FilterRegister
*/
typedef struct
{
__IO uint32_t FR1;
__IO uint32_t FR2;
}CAN_Filter Register_TypeDef;CAN硬件过滤器工作模式、访问码和访问码掩码。 通过设置CAN过滤器，可以使CAN端口只接收符合规定的的CAN数据包，这样就能将CAN总线划分成若干网段用于支持不同应用。
/**
* @brief Controller Area Network
*/
typedef struct
{
__IO uint32_t MCR;
__IO uint32_t MSR;
__IO uint32_t TSR;
__IO uint32_t RF0R;
__IO uint32_t RF1R;
__IO uint32_t IER;
__IO uint32_t ESR;
__IO uint32_t BTR;
uint32_tRESERVED0[88];
CAN_TxMailBox_TypeDef sTxMailBox[3];
CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
uint32_tRESERVED1[12];
__IO uint32_t FMR;
__IO uint32_t FM1R;
uint32_tRESERVED2;
__IO uint32_t FS1R;
uint32_tRESERVED3;
__IO uint32_t FFA1R;
uint32_tRESERVED4;
__IO uint32_t FA1R;
uint32_tRESERVED5[8];
#ifndef STM32F10X_CL
CAN_FilterRegister_TypeDef sFilterRegister[14];
#else
CAN_FilterRegister_TypeDef sFilterRegister[28];
#endif /* STM32F10X_CL */
} CAN_TypeDef;
/**
* @brief Consumer Electronics Control (CEC)
*/
typedef struct
{
__IO uint32_t CFGR;
__IO uint32_t OAR;
__IO uint32_t PRES;
__IO uint32_t ESR;
__IO uint32_t CSR;
__IO uint32_t TXD;
__IO uint32_t RXD;
} CEC_TypeDef; CEC用于记录CAN总线发送数据错误的计数器
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR;
__IO uint8_tIDR;
uint8_t RESERVED0;
uint16_tRESERVED1;
__IO uint32_t CR;
} CRC_TypeDeCRC校验
/**
* @brief Digital to Analog Converter 数模转换相应的结构体，DAC相关寄存器啊
*/
typedef struct
{
__IO uint32_t CR;
__IO uint32_t SWTRIGR; SWTRIGR 这个DAC软件触发寄存器
__IO uint32_t DHR12R1;DAC 通道 1 的 12 位右对齐数据保持寄存器：DAC_DHR12R1。这个我只讲一个，这里面全部是关于DAC转换的相关寄存器。请大家自行对照硬件手册查找。
__IO uint32_t DHR12L1;
__IO uint32_t DHR8R1;
__IO uint32_t DHR12R2;
__IO uint32_t DHR12L2;
__IO uint32_t DHR8R2;
__IO uint32_t DHR12RD;
__IO uint32_t DHR12LD;
__IO uint32_t DHR8RD;
__IO uint32_t DOR1;
__IO uint32_t DOR2;
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
__IO uint32_t SR;
#endif
} DAC_TypeDef;
/**
*@briefDMA Controller DMA传输将数据从一个地址空间复制到另外一个地址空间。当CPU初始化这个传输动作，传输动作本身是由DMA控制器来实行和完成。典型的例子就是移动一个外部内存的区块到芯片内部更快的内存区。像是这样的操作并没有让处理器工作拖延，反而可以被重新排程去处理其他的工作。DMA传输对于高效能 嵌入式系统算法和网络是很重要的。
DMA 在实现DMA传输时，是由DMA控制器直接掌管总线，因此，存在着一个总线控制权转移问题。即DMA传输前，CPU要把总线控制权交给DMA控制器，而在结束DMA传输后，DMA控制器应立即把总线控制权再交回给CPU。一个完整的DMA传输过程必须经过DMA请求、DMA响应、DMA传输、DMA结束4个步骤。 */
typedef struct 这里就是直接内存寻址寄存器相关定义，我想DMA大家应该不是太陌生。
{
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
} DMA_Channel_TypeDef;
typedef struct
{
__IO uint32_t ISR;
__IO uint32_t IFCR;
} DMA_TypeDef;
/**
*@briefEthernet MAC
*/MAC(Medium Access Control)模块，实现符合IEEE 802.3标准的MAC逻辑。 这个结构体是网络模块的相关定义。
typedef struct
{
__IO uint32_t MACCR;
__IO uint32_t MACFFR;
__IO uint32_t MACHTHR;
__IO uint32_t MACHTLR;
__IO uint32_t MACMIIAR;
__IO uint32_t MACMIIDR;
__IO uint32_t MACFCR;
__IO uint32_t MACVLANTR;/* 8 */
uint32_t RESERVED0[2];
__IO uint32_t MACRWUFFR;/* 11 */
__IO uint32_t MACPMTCSR;
uint32_t RESERVED1[2];
__IO uint32_t MACSR;/* 15 */
__IO uint32_t MACIMR;
__IO uint32_t MACA0HR;
__IO uint32_t MACA0LR;
__IO uint32_t MACA1HR;
__IO uint32_t MACA1LR;
__IO uint32_t MACA2HR;
__IO uint32_t MACA2LR;
__IO uint32_t MACA3HR;
__IO uint32_t MACA3LR;/* 24 */
uint32_t RESERVED2[40];
__IO uint32_t MMCCR;/* 65 */
__IO uint32_t MMCRIR;
__IO uint32_t MMCTIR;
__IO uint32_t MMCRIMR;
__IO uint32_t MMCTIMR;/* 69 */
uint32_t RESERVED3[14];
__IO uint32_t MMCTGFSCCR; /* 84 */
__IO uint32_t MMCTGFMSCCR;
uint32_t RESERVED4[5];
__IO uint32_t MMCTGFCR;
uint32_t RESERVED5[10];
__IO uint32_t MMCRFCECR;
__IO uint32_t MMCRFAECR;
uint32_t RESERVED6[10];
__IO uint32_t MMCRGUFCR;
uint32_t RESERVED7[334];
__IO uint32_t PTPTSCR;
__IO uint32_t PTPSSIR;
__IO uint32_t PTPTSHR;
__IO uint32_t PTPTSLR;
__IO uint32_t PTPTSHUR;
__IO uint32_t PTPTSLUR;
__IO uint32_t PTPTSAR;
__IO uint32_t PTPTTHR;
__IO uint32_t PTPTTLR;
uint32_t RESERVED8[567];
__IO uint32_t DMABMR;
__IO uint32_t DMATPDR;
__IO uint32_t DMARPDR;
__IO uint32_t DMARDLAR;
__IO uint32_t DMATDLAR;
__IO uint32_t DMASR;
__IO uint32_t DMAOMR;
__IO uint32_t DMAIER;
__IO uint32_t DMAMFBOCR;
uint32_t RESERVED9[9];
__IO uint32_t DMACHTDR;
__IO uint32_t DMACHRDR;
__IO uint32_t DMACHTBAR;
__IO uint32_t DMACHRBAR;
} ETH_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/ EXTI寄存器结构
EXTI寄存器结构，EXTI_TypeDef，在文件stm2f10x_map.h中定义如下： typedef struct{ vu32 IMR; vu32 EMR; vu32 RTSR; vu32 FTSR; vu32 SWIER; vu32 PR; }EXTI_TypeDef; Table 128.例举了EXTI所有寄存器 Table 128. EXTI寄存器 寄存器 描述IMR中断屏蔽寄存器EMR事件屏蔽寄存器RTSR上升沿触发选择寄存器FTSR下降沿触发选择寄存器SWIR软件中断事件寄存器PR挂起寄存器
typedef struct
{
__IO uint32_t IMR;
__IO uint32_t EMR;
__IO uint32_t RTSR;
__IO uint32_t FTSR;
__IO uint32_t SWIER;
__IO uint32_t PR;
} EXTI_TypeDef;
/**
* @brief FLASH Registers
*/ FLASH寄存器 寄存器 描述ACR FLASH访问控制寄存器KEYR FPEC密钥寄存器OPTKEYR选择字节密钥寄存器SR FLASH状态寄存器CR FLASH控制寄存器AR FLASH地址寄存器OBR选择字节和状态寄存器WRPR选择字节写保护寄存器 typedef struct
{
__IO uint32_t ACR;
__IO uint32_t KEYR;
__IO uint32_t OPTKEYR;
__IO uint32_t SR;
__IO uint32_t CR;
__IO uint32_t AR;
__IO uint32_t RESERVED;
__IO uint32_t OBR;
__IO uint32_t WRPR;
#ifdef STM32F10X_XL
uint32_t RESERVED1[8];
__IO uint32_t KEYR2;
uint32_t RESERVED2;
__IO uint32_t SR2;
__IO uint32_t CR2;
__IO uint32_t AR2;
#endif /* STM32F10X_XL */
} FLASH_TypeDef;
***************************************************
//本程序只供学习使用，如果用于工程应用，请仔细检查
//主要对于ST公司的库存文件stm32f10x.h进行解析
//修改日期:/6
//Copyright(C) -2025
//All rights reserved
//*********************************************************************************/
/**
*@briefReal-Time Clock
*/
RTC预分频器余数寄存器高位(RTC_DIVH)
RTC预分频器余数寄存器低位(RTC_DIVL)
RTC控制寄存器高位(RTC_CRH)
RTC控制寄存器低位(RTC_CRL)
RTC预分频装载寄存器高位(RTC_PRLH)
RTC预分频装载寄存器低位(RTC_PRLL)
RTC计数器寄存器高位(RTC_CNTH)
RTC计数器寄存器低位(RTC_CNTL)
RTC闹钟寄存器高位(RTC_ALRH)
RTC闹钟寄存器低位(RTC_ALRL)
typedef struct
{
__IO uint16_t CRH;
uint16_tRESERVED0; RTC寄存器是16位可寻址寄存器，这是定义它的数据类型为16位的。
__IO uint16_t CRL;
uint16_tRESERVED1;
__IO uint16_t PRLH;
uint16_tRESERVED2;
__IO uint16_t PRLL;
uint16_tRESERVED3;
__IO uint16_t DIVH;
uint16_tRESERVED4;
__IO uint16_t DIVL;
uint16_tRESERVED5;
__IO uint16_t CNTH;
uint16_tRESERVED6;
__IO uint16_t CNTL;
uint16_tRESERVED7;
__IO uint16_t ALRH;
uint16_tRESERVED8;
__IO uint16_t ALRL;
uint16_tRESERVED9;
}
RTC_TypeDef;
/**
* @brief SD host InterfaceSD卡接口
*/
SDIO电源控制寄存器(SDIO_POWER)
SDIO时钟控制寄存器(SDIO_CLKCR)
SDIO参数寄存器(SDIO_ARG)
SDIO命令寄存器(SDIO_CMD)
SDIO命令响应寄存器(SDIO_RESPCMD)
SDIO响应1..4寄存器(SDIO_RESPx)
SDIO数据定时器寄存器(SDIO_DTIMER)
SDIO数据长度寄存器(SDIO_DLEN)
SDIO数据控制寄存器(SDIO_DCTRL)
SDIO数据计数器寄存器(SDIO_DCOUNT)
SDIO状态寄存器(SDIO_STA)
SDIO清除中断寄存器(SDIO_ICR)
SDIO中断屏蔽寄存器(SDIO_MASK)
SDIO FIFO计数器寄存器(SDIO_FIFOCNT)
SDIO数据FIFO寄存器(SDIO_FIFO)
typedef struct
{
__IO uint32_t POWER;
__IO uint32_t CLKCR;
__IO uint32_t ARG;
__IO uint32_t CMD;
__I uint32_t RESPCMD;
__I uint32_t RESP1;
__I uint32_t RESP2;
__I uint32_t RESP3;
__I uint32_t RESP4;
__IO uint32_t DTIMER;
__IO uint32_t DLEN;
__IO uint32_t DCTRL;
__I uint32_t DCOUNT;
__I uint32_t STA;
__IO uint32_t ICR;
__IO uint32_t MASK;
uint32_tRESERVED0[2];
__I uint32_t FIFOCNT;
uint32_tRESERVED1[13];
__IO uint32_t FIFO;
} SDIO_TypeDef;
/**
* @brief Serial Peripheral Interface-------------SPI串行总线
*/
SPI控制寄存器1(SPI_CR1)
SPI控制寄存器2(SPI_CR2)
SPI 状态寄存器(SPI_SR)
SPI 数据寄存器(SPI_DR)
SPI CRC多项式寄存器(SPI_CRCPR)
SPI Rx CRC寄存器(SPI_RXCRCR)
SPI Tx CRC寄存器(SPI_TXCRCR)
SPI_I2S配置寄存器(SPI_I2S_CFGR)
SPI_I2S预分频寄存器(SPI_I2SPR)
typedef struct
{
__IO uint16_t CR1;
uint16_tRESERVED0;
__IO uint16_t CR2;
uint16_tRESERVED1;
__IO uint16_t SR;
uint16_tRESERVED2;
__IO uint16_t DR;
uint16_tRESERVED3;
__IO uint16_t CRCPR;
uint16_tRESERVED4;
__IO uint16_t RXCRCR;
uint16_tRESERVED5;
__IO uint16_t TXCRCR;
uint16_tRESERVED6;
__IO uint16_t I2SCFGR;
uint16_tRESERVED7;
__IO uint16_t I2SPR;
uint16_tRESERVED8;
} SPI_TypeDef;
/**
* @brief TIM
高级控制定时器(TIM1和TIM8)由一个16位的自动装载计数器组成，它由一个可编程的预分频器驱动。
它适合多种用途，包含测量输入信号的脉冲宽度(输入捕获)，或者产生输出波形(输出比较、
PWM、嵌入死区时间的互补PWM等)。
使用定时器预分频器和RCC时钟控制预分频器，可以实现脉冲宽度和波形周期从几个微秒到几
个毫秒的调节。
高级控制定时器(TIM1和TIM8)和通用定时器(TIMx)是完全独立的，它们不共享任何资源。它们
可以同步操作.
控制寄存器1(TIMx_CR1)
控制寄存器2(TIMx_CR2)
从模式控制寄存器(TIMx_SMCR)
DMA/中断使能寄存器(TIMx_DIER)
状态寄存器(TIMx_SR)
事件产生寄存器(TIMx_EGR)
捕获/比较模式寄存器1(TIMx_CCMR1)
捕获/比较模式寄存器2(TIMx_CCMR2)
捕获/比较使能寄存器(TIMx_CCER)
计数器(TIMx_CNT)
预分频器(TIMx_PSC)
自动重装载寄存器(TIMx_ARR)
重复计数寄存器(TIMx_RCR)
捕获/比较寄存器1(TIMx_CCR1)
捕获/比较寄存器2(TIMx_CCR2)
捕获/比较寄存器3(TIMx_CCR3)
捕获/比较寄存器(TIMx_CCR4)
刹车和死区寄存器(TIMx_BDTR)
DMA控制寄存器(TIMx_DCR)
连续模式的DMA地址(TIMx_DMAR)
这个结构体就是以上这些寄存器的类型定义。
*/
typedef struct
{
__IO uint16_t CR1;
uint16_tRESERVED0;
__IO uint16_t CR2;
uint16_tRESERVED1;
__IO uint16_t SMCR;
uint16_tRESERVED2;
__IO uint16_t DIER;
uint16_tRESERVED3;
__IO uint16_t SR;
uint16_tRESERVED4;
__IO uint16_t EGR;
uint16_tRESERVED5;
__IO uint16_t CCMR1;
uint16_tRESERVED6;
__IO uint16_t CCMR2;
uint16_tRESERVED7;
__IO uint16_t CCER;
uint16_tRESERVED8;
__IO uint16_t CNT;
uint16_tRESERVED9;
__IO uint16_t PSC;
uint16_tRESERVED10;
__IO uint16_t ARR;
uint16_tRESERVED11;
__IO uint16_t RCR;
uint16_tRESERVED12;
__IO uint16_t CCR1;
uint16_tRESERVED13;
__IO uint16_t CCR2;
uint16_tRESERVED14;
__IO uint16_t CCR3;
uint16_tRESERVED15;
__IO uint16_t CCR4;
uint16_tRESERVED16;
__IO uint16_t BDTR;
uint16_tRESERVED17;
__IO uint16_t DCR;
uint16_tRESERVED18;
__IO uint16_t DMAR;
uint16_tRESERVED19;
} TIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/在UART上追加同步方式的序列信号变换电路的产品，被称为USART(Universal Synchronous Asynchronous Receiver Transmitter)。
状态寄存器(USART_SR)
数据寄存器(USART_DR)
波特比率寄存器(USART_BRR)
控制寄存器1(USART_CR1)
控制寄存器2(USART_CR2)
控制寄存器3(USART_CR3)
保护时间和预分频寄存器(USART_GTPR)
typedef struct
{
__IO uint16_t SR;
uint16_tRESERVED0;
__IO uint16_t DR;
uint16_tRESERVED1;
__IO uint16_t BRR;
uint16_tRESERVED2;
__IO uint16_t CR1;
uint16_tRESERVED3;
__IO uint16_t CR2;
uint16_tRESERVED4;
__IO uint16_t CR3;
uint16_tRESERVED5;
__IO uint16_t GTPR;
uint16_tRESERVED6;
} USART_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR;
__IO uint32_t CFR;
__IO uint32_t SR;
} WWDG_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!<FLASH base address in the alias region
在Alias地区Flash基址*/
#define SRAM_BASE((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
#define TIM2_BASE(APB1PERIPH_BASE + 0x0000)
#define TIM3_BASE(APB1PERIPH_BASE + 0x0400)
#define TIM4_BASE(APB1PERIPH_BASE + 0x0800)
#define TIM5_BASE(APB1PERIPH_BASE + 0x0C00)
#define TIM6_BASE(APB1PERIPH_BASE + 0x1000)
#define TIM7_BASE(APB1PERIPH_BASE + 0x1400)
#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
#define WWDG_BASE(APB1PERIPH_BASE + 0x2C00)
#define IWDG_BASE(APB1PERIPH_BASE + 0x3000)
#define SPI2_BASE(APB1PERIPH_BASE + 0x3800)
#define SPI3_BASE(APB1PERIPH_BASE + 0x3C00)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
#define I2C1_BASE(APB1PERIPH_BASE + 0x5400)
#define I2C2_BASE(APB1PERIPH_BASE + 0x5800)
#define CAN1_BASE(APB1PERIPH_BASE + 0x6400)
#define CAN2_BASE(APB1PERIPH_BASE + 0x6800)
#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
#define AFIO_BASE(APB2PERIPH_BASE + 0x0000)
#define EXTI_BASE(APB2PERIPH_BASE + 0x0400)
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
#define ADC1_BASE(APB2PERIPH_BASE + 0x2400)
#define ADC2_BASE(APB2PERIPH_BASE + 0x2800)
#define TIM1_BASE(APB2PERIPH_BASE + 0x2C00)
#define SPI1_BASE(APB2PERIPH_BASE + 0x3000)
#define TIM8_BASE(APB2PERIPH_BASE + 0x3400)
#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
#define ADC3_BASE(APB2PERIPH_BASE + 0x3C00)
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
#define TIM9_BASE(APB2PERIPH_BASE + 0x4C00)
#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)
#define SDIO_BASE(PERIPH_BASE + 0x18000)
#define DMA1_BASE(AHBPERIPH_BASE + 0x0000)
#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
#define DMA2_BASE(AHBPERIPH_BASE + 0x0400)
#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
#define OB_BASE((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
#define ETH_BASE (AHBPERIPH_BASE + 0x8000)
#define ETH_MAC_BASE (ETH_BASE)
#define ETH_MMC_BASE (ETH_BASE + 0x0100)
#define ETH_PTP_BASE (ETH_BASE + 0x0700)
#define ETH_DMA_BASE (ETH_BASE + 0x1000)
#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
/******************************************************************************/
/*Peripheral Registers_Bits_Definition
、 串行寄存器位定义 */
/******************************************************************************/
/******************************************************************************/
/**/
/* CRC calculation unit*/
/*CRC 校验单元*/
/******************************************************************************/
/*******************Bit definition for CRC_DR register*********************/
#defineCRC_DR_DR ((uint32_t)0xFFFFFFFF)/*!< Data register bits数据寄存器位 */
数据寄存器(CRC_DR)
/*******************Bit definition for CRC_IDR register********************/
#defineCRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits 通用8位寄存器*/
独立数据寄存器(CRC_IDR)
控制寄存器(CRC_CR)
/********************Bit definition for CRC_CR register********************/
#defineCRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit 重启位*/
/******************************************************************************/
/**/
/* Power Control */
/**/
/******************************************************************************/
/********************Bit definition for PWR_CR register********************/
#definePWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */
#definePWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
#definePWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
#definePWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
#definePWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
#definePWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
#definePWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
#definePWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
#definePWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
/*!< PVD level configuration */
#definePWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */
#definePWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */
#definePWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */
#definePWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */
#definePWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */
#definePWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */
#definePWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */
#definePWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */
#definePWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
/*******************Bit definition for PWR_CSR register********************/
#definePWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
#definePWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
#definePWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
#definePWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
/******************************************************************************/
/**/
/*Backup registers*/
/**/
/******************************************************************************/
/*******************Bit definition for BKP_DR1 register********************/
#defineBKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR2 register********************/
#defineBKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR3 register********************/
#defineBKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR4 register********************/
#defineBKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR5 register********************/
#defineBKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR6 register********************/
#defineBKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR7 register********************/
#defineBKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR8 register********************/
#defineBKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR9 register********************/
#defineBKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR10 register*******************/
#defineBKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR11 register*******************/
#defineBKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR12 register*******************/
#defineBKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR13 register*******************/
#defineBKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR14 register*******************/
#defineBKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR15 register*******************/
#defineBKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR16 register*******************/
#defineBKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR17 register*******************/
#defineBKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */
/******************Bit definition for BKP_DR18 register********************/
#defineBKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR19 register*******************/
#defineBKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR20 register*******************/
#defineBKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR21 register*******************/
#defineBKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR22 register*******************/
#defineBKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR23 register*******************/
#defineBKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR24 register*******************/
#defineBKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR25 register*******************/
#defineBKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR26 register*******************/
#defineBKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR27 register*******************/
#defineBKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR28 register*******************/
#defineBKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR29 register*******************/
#defineBKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR30 register*******************/
#defineBKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR31 register*******************/
#defineBKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR32 register*******************/
#defineBKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR33 register*******************/
#defineBKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR34 register*******************/
#defineBKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR35 register*******************/
#defineBKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR36 register*******************/
#defineBKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR37 register*******************/
#defineBKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR38 register*******************/
#defineBKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR39 register*******************/
#defineBKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR40 register*******************/
#defineBKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR41 register*******************/
#defineBKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */
/*******************Bit definition for BKP_DR42 register*******************/
#defineBKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */
/******************Bit definition for BKP_RTCCR register*******************/
#defineBKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */
#defineBKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */
#defineBKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */
#defineBKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */
/********************Bit definition for BKP_CR register********************/
#defineBKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */
#defineBKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */
/*******************Bit definition for BKP_CSR register********************/
#defineBKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */
#defineBKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */
#defineBKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */
#defineBKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */
#defineBKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */
/******************************************************************************/
/**/
/* Reset and Clock Control*/
/**/
/******************************************************************************/
/********************Bit definition for RCC_CR register********************/
#defineRCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
#defineRCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
#defineRCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
#defineRCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
#defineRCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
#defineRCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
#defineRCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
#defineRCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
#defineRCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
#defineRCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
#ifdef STM32F10X_CL
#defineRCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */
#defineRCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */
#defineRCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */
#defineRCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */
#endif /* STM32F10X_CL */
